1. Field of the Invention
The present invention relates to a structure for testing a NAND flash memory and a method of measuring a channel voltage of the NAND flash memory using the same and, more particularly, to a structure for testing a NAND flash memory having a structure capable of measuring a channel voltage, and a method of measuring the channel voltage of the NAND flash memory using the same.
2. Discussion of Related Art
Recently, there is an increasing demand for semiconductor memory devices that are electrically programmed and erased and on which data can be stored without being erased even in a state where the power is not supplied. Further, in order to develop a large-capacity memory device capable of storing a large quantity of data, a high-integration technology of the memory cell has been developed. For this, there was proposed a NAND type flash memory device in which a plurality of memory cells are serially connected to form a single string and a plurality of the strings constitute a single memory cell array.
The flash memory cells of the NAND flash memory device include a current path formed between the source and drain on a semiconductor substrate, and a floating gate and a control gate that are connected over the semiconductor substrate with an insulator intervened between them. Further, the program operation of the flash memory cell is performed by making a source region of the memory cell and the semiconductor substrate, i.e., a bulk region grounded, applying a positive high voltage (program voltage; Vpp, for example 15V to 20V) to the control gate, and a voltage for a program (for example, 5 to 6V) to the drain of the memory cell, in order to generate hot carriers. The hot carriers are generated as electrons of the bulk region are accumulated on the floating gate due to an electric field of the high voltage (Vpp) applied to the control gate and charges supplied to the drain region are continuously accumulated.
The erase operation of the flash memory cell is simultaneously performed in a sector unit sharing the bulk region, by applying a negative high voltage (erase voltage; Vera, for example −10V) to the control gate and applying a given voltage (for example 5V) to the bulk region to cause fowler-nordheim tunneling (F-N tunneling). F-N tunneling causes the electrons accumulated on the floating gate to be discharged toward the source region, so that the flash memory cells has distribution of the erase threshold voltage ranging from about 1V to 3V.
The memory cell the threshold voltage of which was increased by the program operation looks turned off since current is prevented from being injected from the drain region to the source region upon the read operation. The cell the threshold voltage of which was lowered by the erase operation looks turned on since current is injected from the drain region to the source region.
FIG. 1 is a layout view showing a conventional NAND flash memory.
First to sixteenth cell regions Cell-1 to Cell-16 where cells are formed are positioned in a longitudinal direction with them spaced apart. Each of the cell regions is positioned to increase in a horizontal direction. Further, active regions A1 and A2 where the cells are formed are positioned in the longitudinal direction so that they intersect the respective cell regions. Drain select lines DSL1 and DSL2 are positioned at an upper side of the first cell region Cell-1 in the longitudinal direction wherein the drain select lines are positioned to increase in the horizontal direction. The drain select line DSL2 is also used in another upper array. Further, source select lines SSL1 and SSL2 are positioned at a lower side of the sixteenth cell region Cell-16 in the longitudinal direction wherein the source select lines are positioned to increase in the horizontal direction. The source select line SSL2 is also used in another lower array. Drain contacts D1 and D2 are formed at regions where between—the drain select lines DSL1 and DSL2 and the active regions A1 and A2 are intersecting. Source contact S1 and S2 are formed at regions where between—the source select lines SSL1 and SSL2 and the active regions A1 and A2 are intersecting.
FIG. 2 is a schematic cross-sectional view of the NAND flash memory taken along lines A—A in FIG. 1.
A field oxide film 20 is formed in a semiconductor substrate 10 wherein a triple well is formed. First to sixteenth cells c1 to c16 are formed at the semiconductor substrate 10 between the field regions 20. A transistor d for selecting a string is formed at the left side of the first cell c1 wherein a gate of the transistor d is connected to the drain select line DSL1. A transistor s for connecting to a common source line is formed at the right side of the sixteenth cell c16 wherein a gate of the transistor s is connected to the source select line SSL1.
FIG. 3 is a circuit diagram of the NAND flash memory shown in FIG. 1.
The first to sixteenth cells c1 to c16 are serially connected in a first string st1. A drain of the first cell c1 is connected to a first bit line b1 through the string select transistor d. A source of the sixteenth cell c16 is connected to a common source line S1 through the source select transistor s. A second string st2 has the same structure to the first string st1.
Upon a program operation, a voltage of 0V is applied to selected bit lines and Vcc is applied to non-selected bit lines. Further, a voltage (Vpgm) of, for example, 18V is applied to selected word lines, a voltage of, for example, 4.5V is applied to the drain select lines DSL and a voltage of 0V is applied to the source select lines SSL, respectively. A voltage (Vpass) of, for example, 10V is applied to non-selected word lines. The cells that are selected according to these voltage conditions are programmed. However, if Vcc is applied to non-selected strings, i.e., strings for which a program is inhibited so as to prevent program disturbance, Vpass is applied to non-selected word lines and Vpgm is applied to selected word lines, cells in the non-selected string perform a self-boosting operation. At this time, the voltage applied to the string is referred to as a channel boosting voltage, which is usually kept about 6V to 8V. Program disturbance depends on whether the channel voltage is high or low.
FIG. 4 is an equivalent circuit diagram of the non-selected string for calculating the channel boosting voltage.
Referring to FIGS. 3 and 4, the channel boosting voltage can be calculated as follows.
In case of a 16 cell array, the channel boosting voltage (Vch) is:Vch=15K(Vpass−Vchini)−Vth1+K(Vpgm−Vchini−Vth2)+Vchini−Ileak*Tpw/Ctot
where, K=Cono*Cox/(Ctot*(Cono+Cox))=Cini/Ctot
Vchini (transfer bit line voltage)=Vcc−Vt13 select (threshold voltage of a select transistor)
Vth1: Threshold voltage of non-selected cells
Vth2: Threshold voltage of selected cells
Ileak: String leakage current
Cono: ONO capacitance
Cox: Capacitance of tunnel oxide films
Ctot: Total capacitance
The boosting channel voltage calculated by the above equation is about 1 to 9V, which may differ depending on a program condition.
Such a boosting channel voltage plays an important role in deciding cell characteristics. This serves as an important factor in analyzing program disturbance. As this boosting channel voltage can be obtained only through calculation in the prior art, there is a significant difference between an actual value and a calculated value. In a real program, an electric field (Eox) of the tunnel oxide film that causes program disturbance in the program inhibit cell becomes Eox=(Vpgm−Vch+Vth0)Kg/Tox.
where, Vth0; Initial voltage
Kg: ONO coupling ratio
Tox: Thickness of a tunnel-oxide film
As described above, the boosting channel voltage becomes an important factor of program disturbance as a variable of Eox. However, there is a problem that analysis of program disturbance is difficult since the method for measuring the boosting channel voltage is not so easy.